Accelerating Chip Design With Machine Learning

被引：31

作者：

Khailany, Brucek ^{[1
]}

Ren, Haoxing ^{[1
]}

Dai, Steve ^{[2
]}

Godil, Saad ^{[3
]}

Keller, Ben ^{[2
]}

Kirby, Robert ^{[4
]}

Klinefelter, Alicia ^{[1
]}

Venkatesan, Rangharajan ^{[1
]}

Zhang, Yanqing ^{[1
]}

Catanzaro, Bryan ^{[3
]}

Dally, William J. ^{[5
]}

机构：

[1] NVIDIA Corp, Santa Clara, CA 95051 USA

[2] NVIDIA Corp, ASIC & VLSI Res Grp, Santa Clara, CA USA

[3] NVIDIA Corp, Appl Deep Learning Res, Santa Clara, CA USA

[4] NVIDIA Corp, Appl Deep Learning Res Team, Santa Clara, CA USA

[5] NVIDIA Corp, Res, Santa Clara, CA USA

来源：

IEEE MICRO | 2020年 / 40卷 / 06期

关键词：

Chip scale packaging; Computational modeling; Task analysis; Logic gates; Training; Very large scale integration; Data models; Design Methodology; Integrated Circuits; Machine Learning; VLSI;

D O I：

10.1109/MM.2020.3026231

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Recent advancements in machine learning provide an opportunity to transform chip design workflows. We review recent research applying techniques such as deep convolutional neural networks and graph-based neural networks in the areas of automatic design space exploration, power analysis, VLSI physical design, and analog design. We also present a future vision of an AI-assisted automated chip design workflow to aid designer productivity and automate optimization tasks.

引用

页码：23 / 32

页数：10

共 16 条

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