A High Efficiency E-Band CMOS Frequency Doubler With a Compensated Transformer-Based Balun for Matching Enhancement

This letter presents a broadband high efficiency frequency doubler based on a new and effective compensation technique. A transformer based input balun achieves good balanced performance and input matching by the newly invented central capacitor based compensation technique. It demonstrates a peak conversion gain (CG) of -2.5 dB and peak efficiency of 9.7% with a saturated output power of 2.5 dBm at 74 GHz. The doubler exhibits a 3 dB CG bandwidth of 28 GHz from 62 to 90 GHz. The fundamental rejection is larger than 20 dB. The doubler is fabricated in a 65 nm CMOS technology with chip area of 0.6 x 0.45 mm(2) and consumes 9-14 mW power.