A 4.1 GHz Prescaler Using Double Data Throughput E-TSPC Structures

被引：0
|
作者：
de Miranda, Fernando P. H. [1 ]
Navarro, Joao S., Jr.
Van Noije, Wilhelmus A. M. [1 ]
机构：
[1] Univ Sao Paulo, Escola Politecn, BR-05508900 Sao Paulo, Brazil
来源：
SBCCI2007: 20TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN | 2007年
关键词：
Prescaler; TSPC; High Speed Digital Circuit; Low Power;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The design of a dual modulus prescaler 32/33 in a 0.35 mu m CMOS technology is presented. In the circuit the technique called Extended True Single Phase Clock (E-TSPC) was applied. Additionally, some dedicated structures to double the data output rate were also employed. The prescaler was implemented and tested and experimental results indicated that the circuit can reach up to 4.12 GHz with 4.93 mW of power consumption at 3.6 V power supply.
引用
收藏
页码：123 / 127
页数：5
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