INVITED: Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project

被引:84
作者
Ajayi, Tutu [1 ]
Chhabria, Vidya A. [2 ]
Fogaca, Mateus [3 ]
Hashemi, Soheil [4 ]
Hosny, Abdelrahman [4 ]
Kahng, Andrew B. [5 ]
Kim, Minsoo [5 ]
Lee, Jeongsup [1 ]
Mallappa, Uday [5 ]
Neseem, Marina [4 ]
Pradipta, Geraldo [2 ]
Reda, Sherief [4 ]
Saligane, Mehdi [1 ]
Sapatnekar, Sachin S. [2 ]
Sechen, Carl [6 ]
Shalan, Mohamed [7 ]
Swartz, William [6 ]
Wang, Lutong [5 ]
Wang, Zhehong [1 ]
Woo, Mingyu [5 ]
Xu, Bangqi [5 ]
机构
[1] Univ Michigan, Ann Arbor, MI 48109 USA
[2] Univ Minnesota, Minneapolis, MN 55455 USA
[3] PGMicro UFRGS, Porto Alegre, RS, Brazil
[4] Brown Univ, Providence, RI 02912 USA
[5] Univ Calif San Diego, La Jolla, CA USA
[6] Univ Texas Dallas, Richardson, TX 75083 USA
[7] Amer Univ Cairo, Cairo, Egypt
来源
PROCEEDINGS OF THE 2019 56TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC) | 2019年
关键词
D O I
10.1145/3316781.3326334
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
We describe the planned Alpha release of OpenROAD, an open-source end-to-end silicon compiler. OpenROAD will help realize the goal of "democratization of hardware design", by reducing cost, expertise, schedule and risk barriers that confront system designers today. The development of open-source, self-driving design tools is in and of itself a "moon shot" with numerous technical and cultural challenges. The open-source flow incorporates a compatible open-source set of tools that span logic synthesis, floorplanning, placement, clock tree synthesis, global routing and detailed routing. The flow also incorporates analysis and support tools for static timing analysis, parasitic extraction, power integrity analysis, and cloud deployment. We also note several observed challenges, or "lessons learned", with respect to development of open-source EDA tools and flows.
引用
收藏
页数:4
相关论文
共 15 条
  • [1] Fixed-outline floorplanning: Enabling hierarchical design
    Adya, SN
    Markov, IL
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2003, 11 (06) : 1120 - 1135
  • [2] Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees
    Alpert, Charles J.
    Chow, Wing-Kai
    Han, Kwangsoo
    Kahng, Andrew B.
    Li, Zhuo
    Liu, Derong
    Venkatesh, Sriram
    [J]. PROCEEDINGS OF THE 2018 INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN (ISPD'18), 2018, : 10 - 17
  • [3] [Anonymous], 2018, P ICCAD
  • [4] Caldwell AE, 2002, IEEE DES TEST COMPUT, V19, P72
  • [5] Chan Wei-Ting Jonas, 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD), P153, DOI 10.1109/ICCD.2014.6974675
  • [6] RePlAce: Advancing Solution Quality and Routability Validation in Global Placement
    Cheng, Chung-Kuan
    Kahng, Andrew B.
    Kang, Ilgweon
    Wang, Lutong
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2019, 38 (09) : 1717 - 1730
  • [7] BoxRouter 2.0: Architecture and implementation of a hybrid and robust global router
    Cho, Minsik
    Lu, Katrina
    Yuan, Kun
    Pan, David Z.
    [J]. IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2, 2007, : 503 - 508
  • [8] Chodorow K., 2013, MongoDB: The Definitive Guide: Powerful and Scalable Data Storage
  • [9] FLUTE: Fast lookup table based rectilinear Steiner minimal tree algorithm for VLSI design
    Chu, Chris
    Wong, Yiu-Chung
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2008, 27 (01) : 70 - 83
  • [10] Fogaça M, 2016, IEEE I C ELECT CIRC, P620, DOI 10.1109/ICECS.2016.7841278