The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm

被引：0

作者：

Mohd, Bassam

Swartzlander, Earl E., Jr.

Aziz, Adnan

机构：

来源：

VLSI-SOC: ADVANCED TOPICS ON SYSTEMS ON A CHIP | 2009年 / 291卷

关键词：

HIGH-PERFORMANCE; COMPLEX; POWER;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This chapter examines the superscalar pipeline Fast Fourier Transform algorithm and architecture. The algorithm presents a memory management scheme that avoids memory contention throughout the pipeline stages. The fundamental algorithm, a switch-based FFT pipeline architecture and an example 64-point FFT implementation are presented. The pipeline consists of log(2)N stages, where N is number of FFT points. Each stage can have M Processing Elements (PEs.) As a result. the architecture speed up is M*log(2)N. The pipeline algorithm is configurable to any M > 1.

引用

页码：227 / 248

页数：22