A New Frequency Comparator for Using in Fast Charge Pump PLLs

被引：0

作者：

Sadeghi, Vahideh Sadat ^{[1
]}

Naimi, Hossein Miar ^{[1
]}

机构：

[1] Babol Univ Technol, Integrated Circuit Res Lab, Babol Sar, Iran

来源：

2013 21ST IRANIAN CONFERENCE ON ELECTRICAL ENGINEERING (ICEE) | 2013年

关键词：

Charge pump PLL; BBFC; fast locking;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A bang-bang frequency comparator (BBFC) can be used in the feedthrough path in pump phase locked loops (CPPLL) to increase the locking speed. In this paper, we present a new structure which can be used as a BBFC and then show how this frequency comparator can decrease the settling time in a charge pump PLL. Simulations in Advanced Design System (ADS2008) using TSMC RF CMOS 0.18um confirm that applying the suggested BBFC can increase the locking speed significantly.

引用

页数：3