A high-speed silicon single-electron random access memory

被引：6

作者：

Stone, NJ ^{[1
]}

Ahmed, I

Nakazato, K

机构：

[1] Cavendish Lab, Microelect Res Ctr, Cambridge CB3 OHE, England

[2] Univ Cambridge, Cavendish Lab, Hitachi Cambridge Lab, Cambridge CB3 0HE, England

来源：

IEEE ELECTRON DEVICE LETTERS | 1999年 / 20卷 / 11期

关键词：

D O I：

10.1109/55.798051

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A silicon random access memory using a single-electron tunnelling transistor (SETT) in the form of a multiple tunnel junction (MTJ) in a silicon nanowire has been assessed in terms of its write speed, retention time, and selectivity at an operating temperature of 4.2 K.

引用

页码：583 / 585

页数：3

共 7 条

[1] THE MULTIPLE-TUNNEL JUNCTION AND ITS APPLICATION TO SINGLE-ELECTRON MEMORY AND LOGIC-CIRCUITS [J].

NAKAZATO, K ;

AHMED, H .

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1995, 34 (2B) :700-706

[2] SINGLE-ELECTRON MEMORY [J].

NAKAZATO, K ;

BLAIKIE, RJ ;

AHMED, H .

JOURNAL OF APPLIED PHYSICS, 1994, 75 (10) :5123-5134

[3] Gate controlled Coulomb blockade effects in the conduction of a silicon quantum wire [J].

Smith, RA ;

Ahmed, H .

JOURNAL OF APPLIED PHYSICS, 1997, 81 (06) :2699-2703

[4] Silicon single electron memory cell [J].

Stone, NJ ;

Ahmed, H .

APPLIED PHYSICS LETTERS, 1998, 73 (15) :2134-2136

[5] Silicon single-electron memory structure [J].

Stone, NJ ;

Ahmed, H .

MICROELECTRONIC ENGINEERING, 1998, 42 :511-514

[6]

Tiwari S, 1996, APPL PHYS LETT, V68, P1377, DOI 10.1063/1.116085

[7]

Yano K., 1993, International Electron Devices Meeting 1993. Technical Digest (Cat. No.93CH3361-3), P541, DOI 10.1109/IEDM.1993.347292

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