Hardware building blocks of a mixed granularity reconfigurable system-on-chip platform

被引:0
作者
Masselos, K [1 ]
Blionas, S
Mignolet, JY
Foster, A
Soudris, D
Nikolaidis, S
机构
[1] INTRACOM SA, Peania 19002, Greece
[2] IMEC, B-3001 Louvain, Belgium
[3] ST Microelect Belgium, Zaventem, Belgium
[4] Democritus Univ Thrace, GR-67100 Xanthi, Greece
[5] Aristotle Univ Thessaloniki, GR-54006 Thessaloniki, Greece
来源
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION | 2004年 / 3254卷
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Due to the combination of flexibility and realization efficiency, reconfigurable hardware has become a promising implementation alternative. In the context of the IST-AMDREL project, a mixed granularity reconfigurable SoC platform targeting wireless communication systems has been developed. The platform's main building blocks are presented, including coarse grain reconfigurable unit, embedded FPGA, interconnection network and application specific reusable blocks. The combination of these blocks in platform instances is expected to lead to a good balance between implementation efficiency and flexibility. An AMDREL platform based reconfigurable SoC for a multi-mode wireless networking system is currently under development.
引用
收藏
页码:613 / 622
页数:10
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