Repeater stage timing analysis for VLSI resistive interconnects

Purpose - In this paper output voltage waveform of CMOS repeater driven VLSI long interconnects is analysed, for deep submicron technologies. Ramp inputs are considered in the analysis as these are more practical than step inputs. Design/methodology/approach - Analytical models are developed for the time dependence of output voltage of repeater driven interconnect loads for rising as well as falling ramp input signals. The interconnect is modelled as a resistive-capacitive load. Various operating regions of the MOSFETs are considered in the models. Method has also been given for determining the time at which MOSFET transits from saturation to linear region. Findings - A good agreement between the analytical and SPICE results is obtained, with analytical error 3 per cent at the most. The models developed work accurately for scaled-supply voltages too. For a repeater loaded interconnect the variation of 90 per cent delay with number of repeaters at different supply voltages has also been determined by the proposed model. It is found that the optimum number of repeaters decreases with voltage-scaling and this decrease is technology independent. Research limitations/implications - The parasitic inductance component in long interconnects is not considered in this analysis. Practical implications - The work is useful for timing analysis of repeater driven resistive interconnects. Originality/value - A very concise analytical approach for a CMOS repeater stage timing analysis is developed.