Comprehensive analysis of Subthreshold short channel behavior of a Dual-material gate strained trapezoidal FinFET

被引：4

作者：

Banerjee, Pritha ^{[1
]}

Sarkar, Subir Kumar ^{[1
]}

机构：

[1] Jadavpur Univ, Dept Elect & Telecommun Engn, Kolkata 700032, India

来源：

SUPERLATTICES AND MICROSTRUCTURES | 2018年 / 117卷

关键词：

Trapezoidal FinFET; Strained Silicon; Short channel effects; Subthreshold swing; Threshold voltage roll-off;

D O I：

10.1016/j.spmi.2018.02.034

中图分类号：

O469 [凝聚态物理学];

学科分类号：

070205 ;

摘要：

The current research highlights the subthreshold short channel characteristics of a novel structure namely Dual-material gate strained Trapezoidal strained FinFET. Based on the effective channel width and equivalent number of gates (ENG), we have developed a quasi 3-D scaling length model and examined device characteristics like potential and electric field. The response of the device towards the various short channel effects has also been studied in depth. The analytical results obtained have been verified using 3-D numerical device simulation results. (C) 2018 Elsevier Ltd. All rights reserved.

引用

页码：527 / 537

页数：11

共 14 条

[1] 3-D analytical modeling of high-k gate stack dual-material tri-gate strained silicon-on-nothing MOSFET with dual-material bottom gate for suppressing short channel effects
Banerjee, Pritha
Sarkar, Subir Kumar
[J]. JOURNAL OF COMPUTATIONAL ELECTRONICS, 2017, 16 (03) : 631 - 639
[2] Basak S., 2014, IEEE P INT C REC ADV
[3] Cartwright J., Nature News, DOI DOI 10.1038/NEWS.2011.274
[4] A Quasi-Two-Dimensional Threshold Voltage Model for Short-Channel Junctionless Double-Gate MOSFETs
Chiang, Te-Kuang
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (09) : 2284 - 2289
[5] D'Agostino F., 2000, Introduction to VLSI design EECS 467
[6] Work Function Engineering With Linearly Graded Binary Metal Alloy Gate Electrode for Short-Channel SOI MOSFET
Deb, Sanjoy
Singh, N. Basanta
Islam, Nurul
Sarkar, Subir Kumar
[J]. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2012, 11 (03) : 472 - 478
[7] A Quasi-3-D Scaling Length Model for Trapezoidal FinFET and Its Application to Subthreshold Behavior Analysis
Gao, Hong-Wun
Wang, Yeong-Her
Chiang, Te-Kuang
[J]. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2017, 16 (02) : 281 - 289
[8] Goel Ekta, 2016, IEEE T ELECT DEV, V63
[9] Kumar M. J., 2006, IEEE T ELECT DEV, V53
[10] An analytical model of threshold voltage for short-channel double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs
Kumar, Mirgender
Dubey, Sarvesh
Tiwari, Pramod Kumar
Jit, S.
[J]. JOURNAL OF COMPUTATIONAL ELECTRONICS, 2013, 12 (01) : 20 - 28

← 1 2 →