Algorithms Based on All-Digital Phase-Locked Loop for Fast-locking and spur Free

Settling time and spur of phase-locked loop (PLL) are important issues in wireless communication systems and worth to be studied. In order to reduce settling time and mitigate spurs in all-digital PLL, some algorithms are presented. The proposed fast-locking algorithm adopts optimized AFC (automatic frequency control) technique with dynamic bandwidth method that doesn't need to calibrate circuits compared to conventional OTW (oscillator turning word) estimating method. A Multi-bits LSB Dithering module is proposed to further suppress fractional spur caused by SDM (sigma-delta modulator) periodic output. A DEM module is applied to weaken the nonlinearity resulted from varactor mismatch and therefore improve the spur performance. Simulation results show that the improvement of settling time is about 27%similar to 72% compared to the ADPLL without fast-locking algorithms. The spur free algorithms are also verified.