MRONoC: A Low Latency and Energy Efficient on Chip Optical Interconnect Architecture

The circuit switched optical network on chip (ONoC) is popularly employed since the optical buffer is not available. However, this technique suffers from limited transmission bandwidth, high setup-time overhead, and high network resource contention, which consequentially induces long latency and degraded throughput. In this paper, we propose a new ONoC architecture aiming at ultralow setup cost, improved scalability, and contention-free communication. We first utilize wavelength division multiplexing (WDM) to introduce the basic version of this ONoC with efficient wavelength assignment. A series of potential versions are developed by using multiple waveguides to relieve the pressure on the number of wavelengths. These potential versions can make a tradeoff between required wavelengths and waveguides and improve the scalability. The new architectures employ two layers relying on the interlayer coupler, which contributes to the decrease of crossing losses. The simulation results show that the architecture can achieve 133% saturated bandwidth improvement compared with the traditional mesh ONoC employing WDM technology under the uniform traffic pattern.