2-Channel Time-Interleaved ADC Frequency Response Mismatch Correction Using Adaptive I/Q Signal Processing

被引:0
作者
Singh, Simran [1 ]
Epp, Michael [1 ]
Vallant, Georg [1 ]
Valkama, Mikko [2 ]
Anttila, Lauri [2 ]
机构
[1] Cassidian, Woerthstr 85, D-89077 Ulm, Germany
[2] Tampere Univ Technol, Dept Elect & Commun Engn, Tampere, Finland
来源
2013 IEEE 56TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) | 2013年
基金
芬兰科学院;
关键词
COMPENSATION; CONVERTERS; ERRORS;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A novel adaptive compensation architecture for the frequency response mismatch of 2-channel Time-Interleaved ADC (TI-ADC) is proposed for developing high-yield self-adaptive systems. The proposed approach overcomes the existing methods in the sense that the TI-ADC mismatch identification can be performed without allocating a region where only the TI-ADC mismatch spurs are present. This is accomplished via mapping the TI-ADC problem into an I/Q mismatch problem which allows deploying complex statistical signal processing. As proof of the concept, the compensation architecture is demonstrated and tested on RF-sampling TI-ADC hardware data.
引用
收藏
页码:1079 / 1084
页数:6
相关论文
共 24 条
[1]  
[Anonymous], 2013, European Patent Application, Patent No. [13 001 057.2, 130010572]
[2]  
[Anonymous], 2012, ADC12D1800RF 12 BIT
[3]  
ANTTILA L, 2007, P IEEE INT C AC SPEE
[4]  
ANTTILA L, 2011, P 17 IEEE EUR WIR C
[5]  
ANTTILA L, 2006, P IEEE INT S PERS IN
[6]   Circularity-based I/Q imbalance compensation in wideband direct-conversion receivers [J].
Anttila, Lauri ;
Valkama, Mikko ;
Renfors, Markku .
IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, 2008, 57 (04) :2099-2113
[7]   TIME INTERLEAVED CONVERTER ARRAYS [J].
BLACK, WC ;
HODGES, DA .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1980, 15 (06) :1022-1029
[8]   Iterative Built-In Testing and Tuning of Mixed-Signal/RF Systems [J].
Chatterjee, A. ;
Han, D. ;
Natarajan, V. ;
Devarakond, S. ;
Sen, S. ;
Choi, H. ;
Senguttuvan, R. ;
Bhattacharya, S. ;
Goyal, A. ;
Lee, D. ;
Swaminathan, M. .
2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 2009, :319-+
[9]  
CHIEN C, DESIGN TEST IEEE
[10]   A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration [J].
El-Chammas, Manar ;
Murmann, Boris .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (04) :838-847