Differential mode input filter design for a three-phase buck-type PWM rectifier based on modeling of the EMC test receiver

被引:108
作者
Nussbaumer, Thomas [1 ]
Heldwein, Marcelo Lobo [1 ]
Kolar, Johann W. [1 ]
机构
[1] Swiss Fed Inst Technol, Power Elect Syst Lab, CH-8092 Zurich, Switzerland
关键词
electromagnetic compatibility (EMC); input filter design; pulsewidth modulation (PWM) rectifier; test receiver;
D O I
10.1109/TIE.2006.881988
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
For a three-phase buck-type pulsewidth modulation rectifier input stage of a high-power telecommunications power supply module, a differential-mode (DM) electromagnetic compatibility (EMC) filter is designed for compliance to CISPR 22 Class B in the frequency range of 150 kHz-30 MHz. The design is based on a harmonic analysis of the rectifier input current and a mathematical model of the measurement procedure including the line impedance stabilization network (LISN) and the test receiver. Guidelines for a successful filter design are given, and components for a 5-kW rectifier prototype are selected. Furthermore, formulas for the estimation of the quasi-peak detector output based on the LISN output voltage spectrum are provided. The damping of filter resonances is optimized for a given attenuation in order to facilitate a higher stability margin for system control. Furthermore, the dependence of the filter input and output impedances and the attenuation characteristic on the inner mains impedance are discussed. As experimentally verified by using a three-phase common-/Differential-Mode separator, this procedure allows accurate prediction of the converter DM conducted emission levels and therefore could be employed in the design process of the rectifier system to ensure compliance to relevant EMC standards.
引用
收藏
页码:1649 / 1661
页数:13
相关论文
共 29 条
[1]  
Albach M., 1986, PESC '86 Record. 17th Annual IEEE Power Electronics Specialists Conference (Cat. No.86CH2310-1), P203
[2]   New wide input voltage range three-phase unity power factor rectifier formed by integration of a three-switch buck-derived front-end and a DC/DC boost converter output stage [J].
Baumann, M ;
Drofenik, U ;
Kolar, JW .
INTELEC(R): TWENTY-SECOND INTERNATIONAL TELECOMMUNICATIONS ENERGY CONFERENCE, 2000, :461-470
[3]  
CHANDRASEKARAN S, 1999, P IEEE PESC 99 JUN, V2, P987
[4]   INTERMEDIATE LINE FILTER DESIGN TO MEET BOTH IMPEDANCE COMPATIBILITY AND EMI SPECIFICATIONS [J].
CHOI, BC ;
CHO, BH .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 1995, 10 (05) :583-588
[5]  
*CISPR, 1977, CISPR PUBL, V16
[6]  
*CISPR, 1993, CISPR PUBL, V22
[7]  
Erich S. Y., 1992, IEEE Transactions on Power Electronics, V7, P143, DOI 10.1109/63.124587
[8]   Optimal single resistor damping of input filters [J].
Erickson, RW .
APEC'99: FOURTEENTH ANNUAL APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION, CONFERENCE PROCEEDINGS, VOLS 1 & 2, 1999, :1073-1079
[9]  
Heldwein ML, 2005, APPL POWER ELECT CO, P797
[10]  
HELDWEIN ML, 2004, P 35 IEEE POW EL SPE