Functional verification of the CMOS S/390 Parallel Enterprise Server G4 system

Verification of the S/390(R) Parallel Enterprise Server G4 processor and level 2 cache, (L2) chips was performed using a different approach than previously, This paper describes the methods employed by our functional verification team to demonstrate that its logical system complied with the S/390 architecture while staying within the changing cost structure and time-to-market constraints, Verification proceeded at four basic levels defined by the breadth of logic being tested, The lowest level, designer macro verification, contained a single designer's hardware description language (in VHDL), Unit-level verification consisted of a logical portion of function that generally contained four or five designers' logic, The third level of verification was the chip level, in which the processor or L2 chips were individually tested, Finally, system-level verification was performed on symmetric multiprocessor (SMP) configurations that included bus-switching network (BSN) chips and I/O connection chips, designated as memory bus adaptors (MBAs), along with multiple copies of the processor and L2 chips.