Direct verification of Quasi-Static Negative Capacitance (QSNC) and its applications

The operating principle of negative capacitance FET (NCFET), which has been spotlighted as a next-generation low-power logic semiconductor device, and the materials and electrical characteristics that NCFETs must have for commercialization, and the demonstrated state-of-art NCFETs, are reviewed and challenges to be overcome are explained. In particular, the possibility of implementing quasi-static negative capacitance ( QSNC), which has been considered as one of the critical problems of NCFETs, is explained from the material and device design point of view. The previously reported improvement in the switching performance of ferroelectric-gated FETs using a ferroelectric film as a gate insulator is analyzed from both QSNC and transient polarization switching perspectives, and an essential verification method to verify the QSNC implementation is presented. Also, QSNC direct verification through polarization extraction from the manufactured NCFET is demonstrated and its validity is confirmed. Finally, through the measurements of the electrical characteristics from nanoscale Fin-NCFETs which have a gate insulator stack (including interlayer + ferroelectric film) with an effective oxide film thickness (EOT) of 1 nm or less, the performance improvement that an NCFET implemented with QSNC can have is confirmed, and by utilizing a fabricated SRAM array composed of Fin- NCFETs, the feasibility of low-power content-addressable memory (CAM) and binary neural network (BNN) applications are experimentally verified.