Resist Profile Simulation with Fast Lithography Model

A traditional approach to construct a fast lithographic model is to match wafer top-down SEM images, contours and/or gauge CDs with a TCC model plus some simple resist representation. This modeling method has been proven and is extensively used for OPC modeling. As the technology moves forward, this traditional approach has become insufficient in regard to lithography weak point detection, etching bias prediction, etc. The drawback of this approach is from metrology and simulation. First, top-down SEM is only good for acquiring planar CD information. Some 3D metrology such as cross-section SEM or AFM is necessary to obtain the true resist profile. Second, the TCC modeling approach is only suitable for planar image simulation. In order to model the resist profile, full 3D image simulation is needed. Even though there are many rigorous simulators capable of catching the resist profile very well, none of them is feasible for full-chip application due to the tremendous consumption of computational resource. The authors have proposed a quasi-3D image simulation method in the previous study [1], which is suitable for full-chip simulation with the consideration of sidewall angles, to improve the model accuracy of planar models.