A pipeline A/D converter architecture with low DNL

A pipeline analog-to-digital converter architecture can reduce the differential nonlinearity (DNL) with a swapping capacitor technique without involving special calibration techniques. An implementation of the overrange stages in the analog pipeline suitable for high-speed applications is proposed. A 14-bit 5-MSample/s converter has been fabricated in a double-poly 0.5-mu m CMOS process. The 3.3 x 3.3 mm(2) chip dissipates 320 mW from a single 5-V supply and achieves a signal-to-noise ratio of 79 dB, a dynamic range of 82 dB, and a DNL below 0.4 LSB.