Strain-Enhanced Performance of Si-Nanowire FETs

被引：4

作者：

Casse, M. ^{[1
]}

Barraud, S. ^{[1
]}

Coquand, R. ^{[1
,2
,3
]}

Koyama, M. ^{[1
,4
]}

Cooper, D. ^{[1
]}

Vizioz, C. ^{[1
]}

Comboroure, C. ^{[1
]}

Perreau, P. ^{[1
]}

Maffini-Alvaro, V. ^{[1
]}

Tabone, C. ^{[1
]}

Tosti, L. ^{[1
]}

Barnola, S. ^{[1
]}

Delaye, V. ^{[1
]}

Aussenac, F. ^{[1
]}

Ghibaudo, G. ^{[3
]}

Iwai, H. ^{[4
]}

Reimbold, G. ^{[1
]}

机构：

[1] CEA Leti, MINATEC Campus,17 Rue Martyrs, F-38054 Grenoble, France

[2] ST Microelect, F-38926 Crolles, France

[3] INPG MINATEC, IMEP LAHC, F-38016 Grenoble, France

[4] Tokyo Inst Technol, Frontier Res Ctr, Midori Ku, Yokohama, Kanagawa, Japan

来源：

SILICON COMPATIBLE MATERIALS, PROCESSES, AND TECHNOLOGIES FOR ADVANCED INTEGRATED CIRCUITS AND EMERGING APPLICATIONS 3 | 2013年 / 53卷 / 03期

关键词：

CARRIER MOBILITY; ORIENTATION; TRANSISTORS; CMOS;

D O I：

10.1149/05303.0125ecst

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

The combination of a multi-gate architecture and strain engineering is a promising way to fabricate high performance CMOS transistors. In this work we examine the effect of strain in Si nanowire Tri-Gate and Omega-Gate transistors. We present and discuss the results of electrical characterization of these advanced devices, with special attention to the carrier mobility, and to the piezoresistive coefficients.

引用

页码：125 / 136

页数：12

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