Parallelization of brute-force attack on MD5 hash algorithm on FPGA

被引：6

作者：

Gillela, Maruthi ^{[1
]}

Prenosil, Vaclav ^{[2
]}

Reddy, G. Venkat ^{[1
]}

机构：

[1] DRDO, Res Ctr Imarat, Hyderabad, India

[2] Masaryk Univ, Fac Informat, Brno, Czech Republic

来源：

2019 32ND INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2019 18TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID) | 2019年

关键词：

LUT; HDL; GPU; IP core;

D O I：

10.1109/VLSID.2019.00034

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

FPGA implementation of MD5 hash algorithm is faster than its software counterpart, but a pre-image brute-force attack on MD5 hash still needs 2 128 iterations theoretically. This work attempts to improve the speed of the brute-force attack on the MD5 algorithm using hardware implementation. A full 64-stage pipelining is done for MD5 hash generation and three architectures are presented for guess password generation. A 32/34/26-instance parallelization of MD5 hash generator and password generator pair is done to search for a password that was hashed using the MD5 algorithm. Total performance of about 6G trials/second has been achieved using a single Virtex-7 FPGA device.

引用

页码：88 / 93

页数：6