共 50 条
- [21] A scheduler synthesis methodology for joint SW/HW design exploration of SoC Design Automation for Embedded Systems, 2010, 14 : 75 - 103
- [22] Virtual component HW/SW co-design - From system level design exploration to HW/SW implementation SYSTEM-ON-CHIP METHODOLOGIES & DESIGN LANGUAGES, 2001, : 333 - 342
- [24] Adaptive Iterative Improvement GP-based Methodology for HW/SW Co-synthesis of Embedded Systems PROCEEDINGS OF THE 7TH INTERNATIONAL JOINT CONFERENCE ON PERVASIVE AND EMBEDDED COMPUTING AND COMMUNICATION SYSTEMS (PECCS), 2017, : 56 - 59
- [25] Is a unified methodology for system-level design possible? IEEE DESIGN & TEST OF COMPUTERS, 2008, 25 (04): : 346 - 357
- [27] System-level HW/SW co-simulation framework for multiprocessor and multithread SoC 2005 IEEE VLSI-TSA INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION & TEST (VLSI-TSA-DAT), PROCEEDINGS OF TECHNICAL PAPERS, 2005, : 177 - 180
- [28] A new HW/SW co-design methodology to generate a system level platform based on LISA 2005 6th International Conference on ASIC Proceedings, Books 1 and 2, 2005, : 215 - 218
- [29] An ESL Methodology for HW/SW Co-Design of Monitorable Embedded Systems: the "Design for Monitorability" Project - Work-in-Progress PROCEEDINGS OF THE 2020 INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE CODESIGN AND SYSTEM SYNTHESIS (CODES+ISSS), 2019, : 40 - 42
- [30] A flexible hierarchical approach for controlling the system-level design complexity of embedded systems Lecture Notes in Electrical Engineering, 2010, 78 : 25 - 42