High-level synthesis for low power

被引:0
|
作者
Macii, E
机构
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:381 / 393
页数:13
相关论文
共 50 条
  • [21] An efficient low-power binding algorithm in high-level synthesis
    Choi, Y
    Kim, T
    2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV, PROCEEDINGS, 2002, : 321 - 324
  • [22] Live Demonstration: A Low-Power High-Level Synthesis System
    Yeh, Hua-Hsin
    Cheng, Chun-Hua
    Huang, Shih-Hsu
    2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS), 2014, : 165 - 166
  • [23] Power-Management High-Level Synthesis
    Macko, Dominik
    Jelemenska, Katarina
    Cicak, Pavel
    2015 IFIP/IEEE INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC), 2015, : 63 - 68
  • [24] A power management methodology for high-level synthesis
    Lakshminarayana, G
    Raghunathan, A
    Jha, NK
    Dey, S
    ELEVENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1997, : 24 - 29
  • [25] Low Power Methodology for an ASIC design flow based on High-Level Synthesis
    Bin Muslim, Fahad
    Qamar, Affaq
    Lavagno, Luciano
    2015 23RD INTERNATIONAL CONFERENCE ON SOFTWARE, TELECOMMUNICATIONS AND COMPUTER NETWORKS (SOFTCOM), 2015, : 11 - 15
  • [26] A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths
    Del Barrio, Alberto A.
    Memik, Seda Ogrenci
    Molina, Maria C.
    Mendias, Jose M.
    Hermida, Roman
    INTEGRATION-THE VLSI JOURNAL, 2013, 46 (02) : 119 - 130
  • [27] High-level low power FPGA design methodology
    Wolff, FG
    Knieser, MJ
    Weyer, DJ
    Papachristou, CA
    PROCEEDINGS OF THE IEEE 2000 NATIONAL AEROSPACE AND ELECTRONICS CONFERENCE: ENGINEERING TOMORROW, 2000, : 554 - 559
  • [28] Low Power Scheduling in High-level Synthesis using Dual-Vth Library
    Ghandali, Samaneh
    Alizadeh, Bijan
    Navabi, Zainalabedin
    PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015), 2015, : 502 - 506
  • [29] High-Level Synthesis for Minimum-Area Low-Power Clock Gating
    Huang, Shih-Hsu
    Tu, Wen-Pin
    Li, Bing-Hung
    JOURNAL OF INFORMATION SCIENCE AND ENGINEERING, 2012, 28 (05) : 971 - 988
  • [30] IMPACT: A high-level synthesis system for low power control flow intensive circuits
    Khouri, KS
    Lakshminarayana, G
    Jha, NK
    DESIGN, AUTOMATION AND TEST IN EUROPE, PROCEEDINGS, 1998, : 848 - 854