Field programmable gate array implementation of variable common mode injection PWM for three-level inverters

This paper proposes implementation of variable common mode injection pulse width modulation (VCMIPWM) scheme using field programmable gate array (FPGA) for three-level inverters. The waveform quality of the inverter output can be improved using suitable PWM control technique. Optimal harmonic profile may be obtained by centring the middle space vectors in a switching cycle. If the expression of common mode voltage calculated for two-level inverter is applied to multilevel inverter, the middle vectors may not be centred. So, the harmonic performance is poor. There is a need to calculate the amount of common mode injection required to centre the middle space vectors in a switching cycle. The amount of common mode injection depends on the magnitude of the reference vectors. The common mode voltage is calculated for various cases and is injected with the sinusoidal reference vector to produce modified reference vectors. Harmonic performance of fixed common mode injection pulse width modulation (FCMIPWM) and VCMIPWM has been compared with the existing sinusoidal PWM (SPWM). In order to make use of the theoretical advantages of the VCMIPWM, this paper proposes the implementation of this PWM using FPGA. Simulation and experimental results are presented in this paper. (C) 2013 Elsevier Ltd. All rights reserved.