3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems

被引：263
作者：
Lu, Jian-Qiang [1 ,2 ]
机构：
[1] Rensselaer Polytech Inst, Dept Elect Comp & Syst Engn, Troy, NY 12180 USA
[2] Rensselaer Polytech Inst, Ctr Integrated Elect, Troy, NY 12180 USA
来源：
PROCEEDINGS OF THE IEEE | 2009年 / 97卷 / 01期
关键词：
Hyperintegration; InfoTech-NanoTech-BioTech systems; three-dimensional (3-D) integration; through silicon via; wafer alignment; wafer bonding; 3-D packaging; CRITICAL ADHESION ENERGY; INTERCONNECT TECHNOLOGY; PERFORMANCE PREDICTION; 3D; INTEGRATION; PROCESSOR; MEMORY; OPPORTUNITIES; PLACEMENT; STACKING;
D O I：
10.1109/JPROC.2008.2007458
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Three-dimensional (3-D) hype rintegration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components to form highly integrated micro-nano systems. This 3-D hyperintegration is expected to lead to an industry paradigm shift due to its tremendous benefits. Worldwide academic and industrial research activities currently focus on technology innovations, simulation and design, and product prototypes. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of InfoTech-NanoTech-BioTech systems. This paper overviews the 3-D hyperintegration and packaging technologies, including motivations, key technology platforms, status, and perspectives towards commercialization. The challenges associated with the 3-D technologies are addressed, including integration architectures and design tools, yield and cost, thermal and mechanical constraints, and manufacturing infrastructure.
引用
收藏
页码：18 / 30
页数：13
相关论文
共 93 条
[1]   Placement and routing in 3D integrated circuits [J].
Ababei, C ;
Feng, Y ;
Goplen, B ;
Mogal, H ;
Zhang, TP ;
Bazargan, K ;
Sapatnekar, S .
IEEE DESIGN & TEST OF COMPUTERS, 2005, 22 (06) :520-531
[2]  
[Anonymous], 2005, INT TECHN ROADM SEM
[3]  
Bamal M, 2006, IEEE INT INTERC TECH, P202
[4]  
Bancroft A, 2001, HEALTH RISK SOC, V3, P89
[5]  
BERNSTEIN K, 2006, 23 INT VLSI MULT INT
[6]   3D processing technology and its impact on iA32 microprocessors [J].
Black, B ;
Nelson, DW ;
Webb, C ;
Samra, N .
IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS, 2004, :316-318
[7]  
Black B, 2006, INT SYMP MICROARCH, P469
[8]  
BONKOHARA M, 2004, P 3D ARCH SEM INT PA
[9]  
BONKOHARA M, 2007, ENABLING TECHNOLOGIE, V970
[10]  
Burns J., 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), P268, DOI 10.1109/ISSCC.2001.912632
12345678910