All-digital background calibration technique for timing mismatch of time-interleaved ADCs

An all-digital background calibration technique for timing mismatch of Time-Interleaved ADCs (TIADCs) is presented. The timing mismatch is estimated by performing the correlation calculation of the outputs of sub channels in the background, and corrected by an improved fractional delay filter based on Farrow structure. The estimation and correction scheme consists of a feedback loop, which can track and correct the timing mismatch in real time. The proposed technique requires only one filter compared with the bank of adaptive filters which requires (M-1) filters in a M-channel TIADC. In case of a 8 bits four-channel TIADC system, the validity and effectiveness of the calibration algorithm are proved by simulation in MATLAB. The proposed architecture is further implemented and validated on the Altera FPGA board. The synthesized design consumes a few percentages of the hardware resources of the FPGA chip, and the synthesized results show that the calibration technique is effective to mitigate the effect of timing mismatch and enhances the dynamic performance of TIADC system.