Statistical Leakage Estimation of Bounds on Nanometric CMOS Circuits

被引：0
|
作者：
Mendoza Vazquez, Raymundo [1 ]
机构：
[1] Univ Politecn Cataluna, Dept Elect Engn, E-08080 Barcelona, Spain
来源：
DTIS: 2009 4TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA, PROCEEDINGS | 2009年
关键词：
Leakage Currents; Leakage Estimation; Statistical Leakage Bounds; REDUCTION TECHNIQUES; POWER ANALYSIS;
D O I：
10.1109/DTIS.2009.4938024
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this work is presented one method of Statistical Leakage estimation of Bounds in CMOS circuits based on the characterization of standard CMOS cell libraries. The leakage estimation takes in account the correlations (rho) of cells structure, input patters and variations on principal process parameters. Also it was considered the presence of Intra-Die process variations for spatial correlations beta = 1 and 0 <- beta -> 1. For the complete ISCAS85 Benchmark understudy the mu and sigma(2) absolute errors varies between 0.0048 to 0.1278 & 0.0301 to 0.3801 for lower bound and 0.0306 to 0.1247 & 0.0411 to 0.2016 for upper bound.
引用
收藏
页码：58 / 63
页数：6
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