NECoBus: A high-end SOC bus with a portable & low-latency wrapper-based interface mechanism

An NECoBus (internal code name), a bus architecture designed for creating portable yet high-throughput SOCs, is described. Its distinguishing feature is a wrapper-based NECoBus Core Interface (NCI) mechanism: an IP core is designed to communicate with another through the NCI, where the NECoBus includes wrappers to hide bus protocols and the wiring delay from the IP core. Importantly, the NECoBus wrapper employs several latency reduction techniques that can effectively remove the latency penalty induced in the conventional wrapper-based bus design: (1) retry encapsulation, (2) write-buffer switching, (3) early bus request and (4) converter-based multiple bit-width connection. The first implementation of the 32/64 bit NECoBus that has been targeted at a 200-MHz bus cycle using the 0.13-um CMOS processes is described in this paper. Evaluation results demonstrate a 16% throughput improvement, and a 15% and 40% read/write latency reduction by those newly developed techniques.