Design of High Resolution Delta Sigma Modulator in 180 nm CMOS technology

被引：0

作者：

Bonthala, Samarth ^{[1
]}

Uppoor, Yashas ^{[1
]}

Nayak, Ashika ^{[1
]}

Polineni, Sreenivasulu ^{[1
]}

Bhat, M. S. ^{[1
]}

机构：

[1] Natl Inst Technol Karnataka, Dept Elect & Commun Engn, Mangaluru 575025, India

来源：

PROCEEDINGS OF THE 2019 9TH INTERNATIONAL SYMPOSIUM ON EMBEDDED COMPUTING AND SYSTEM DESIGN (ISED 2019) | 2019年

关键词：

Comparator; Cascoding; Delta Sigma ADC; Delta Sigma Modulator; Gain boosting; Operational Transconductance Amplifier; Switched Capacitor Integrator; FREQUENCY COMPENSATION; POWER;

D O I：

10.1109/ised48680.2019.9096220

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents the design and simulation of a Delta Sigma Modulator (DSM) to be employed in a Delta Sigma Analog to Digital Converter. The designed modulator block comprises of a high gain Operational Transconductance Amplifier (OTA) of the folded cascode type providing a DC gain of 91dB and phase margin of 60 degrees which is better than previously published results [3], [8], [5] in the similar domain. Signal to Quantization Noise ratio of 79.96 dB is obtained corresponding to an effective number of bits of 13 for a signal bandwidth of 2kHz and an oversampling ratio (OSR) of 1000, which is suitable for low frequency applications. All the necessary blocks are designed using UMC 180nm CMOS 1P9M technology with supply voltage of 1.8 V.

引用

页码：78 / 83

页数：6

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