An Efficient Clustering Algorithm for Low Power Clock Tree Synthesis

Clocks are known to be major source of power consumption in digital circuits, especially in high performance microprocessors. With the technology scaling, the increasingly capacitive interconnects contribute to more than 40% of the local clock power. In this paper, we propose a clustering algorithm for the minimization of the power in local clock tree, which is shown to be equivalent to the minimization of interconnect capacitance in the tree. Given a set of sequentials and their locations, clustering is performed to determine the clock buffers that are required to synchronize the sequentials, where a cluster implies that a clock buffer drives all the sequentials in the cluster. The clustering algorithm uses minimum spanning tree (MST) metric to estimate the interconnect capacitance and ensures the optimality of the solution, when no capacity constraints are applied. The buffers are then sized and clock nets are routed to minimize the delay, slope, and skew constraints. We compare the clock trees obtained by our clustering and the competitive approaches on several blocks from a microprocessor design in 65 nm technology. The comparison shows that our algorithm improves the clock tree capacitance consistently by up to 21%.