High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives

被引：21

作者：

Lee, Youngjoo ^{[1
]}

Yoo, Hoyoung ^{[1
]}

Yoo, Injae ^{[1
]}

Park, In-Cheol ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Dept Elect Engn, Taejon 305701, South Korea

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2014年 / 22卷 / 05期

关键词：

BCH code; circuit optimization; digital integrated circuits (ICs); flash memory; VLSI; CHIP;

D O I：

10.1109/TVLSI.2013.2264687

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a high-throughput and low-complexity BCH decoder for NAND flash memory applications, which is developed to achieve a high data rate demanded in the recent serial interface standards. To reduce the decoding latency, a data sequence read from a flash memory channel is re-encoded by using the encoder that is idle at that time. In addition, several optimizing methods are proposed to relax the hardware complexity of a massive-parallel BCH decoder and increase the operating frequency. In a 130-nm CMOS process, a (8640, 8192, 32) BCH decoder designed as a prototype provides a decoding throughput of 6.4 Gb/s while occupying an area of 0.85 mm(2).

引用

页码：1183 / 1187

页数：5

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