Analysis of charge loss in nonvolatile memory with multi-layered SiC nanocrystals

被引：22

作者：

Lee, Dong Uk ^{[1
,2
]}

Lee, Tae Hee ^{[1
,2
]}

Kim, Eun Kyu ^{[1
,2
]}

Shin, Jin-Wook ^{[3
]}

Cho, Won-Ju ^{[3
]}

机构：

[1] Hanyang Univ, Dept Phys, Seoul 133791, South Korea

[2] Hanyang Univ, Quantum Funct Spin Lab, Seoul 133791, South Korea

[3] Kwangwoon Univ, Dept Elect Mat Engn, Seoul 139701, South Korea

来源：

APPLIED PHYSICS LETTERS | 2009年 / 95卷 / 06期

基金：

新加坡国家研究基金会;

关键词：

electron traps; hole traps; leakage currents; multilayers; nanoparticles; Poole-Frenkel effect; random-access storage; semiconductor quantum dots; silicon compounds; wide band gap semiconductors; MATRIX; FILMS;

D O I：

10.1063/1.3205112

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

A nonvolatile memory device with multilayered SiC nanocrystals for long-term data storage was fabricated, and its electrical properties were analyzed. The average size and density of the SiC nanocrystals, which were formed between the tunnel and control oxide layers, were approximately 5 nm and 2x10(12) cm(-2), respectively. The memory window of nonvolatile memory with the multilayer of SiC nanocrystals was about 2.5 V after program and erase voltages of +/- 12 V were applied for 500 ms, and then it was maintained at about 1.1 V for 10(5) s at 75 degrees C. The activation energy estimated from charge losses of 25% to 50% increased from 0.03 to 0.30 eV, respectively. The charge loss could be caused by a Pool-Frenkel current of holes and electrons between the SiC quantum dots and the carrier charge traps around the SiC nanocrystals embedded in SiO2 or the degradation effect of the tunnel oxide by stress induced leakage current.

引用

页数：3

共 27 条

[1] Engineering on tunnel barrier and dot surface in Si nanocrystal memories [J].

Baik, SJ ;

Choi, S ;

Chung, UI ;

Moon, JT .

SOLID-STATE ELECTRONICS, 2004, 48 (09) :1475-1481

[2]

Brewer J. J., 2008, NONVOLATILE MEMORY T, P478

[3] Quasisuperlattice storage: A concept of multilevel charge storage [J].

Chang, TC ;

Yan, ST ;

Liu, PT ;

Chen, CW ;

Wu, HH ;

Sze, SM .

APPLIED PHYSICS LETTERS, 2004, 85 (02) :248-250

[4] Fabrication of 50-nm gate SOI n-MOSFETs using novel plasma-doping technique [J].

Cho, WJ ;

Ahn, CG ;

Im, KJ ;

Yang, JH ;

Oh, JH ;

Baek, IB ;

Lee, S .

IEEE ELECTRON DEVICE LETTERS, 2004, 25 (06) :366-368

[5] Charge-transition levels of oxygen vacancy as the origin of device instability in HfO2 gate stacks through quasiparticle energy calculations [J].

Choi, Eun-Ae ;

Chang, K. J. .

APPLIED PHYSICS LETTERS, 2009, 94 (12)

[6] A new extrapolation law for data-retention time-to-failure of nonvolatile memories [J].

De Salvo, B ;

Ghibaudo, G ;

Pananakakis, G ;

Guillaumot, B ;

Candelier, P ;

Reimbold, G .

IEEE ELECTRON DEVICE LETTERS, 1999, 20 (05) :197-199

[7]

DESALVO B, 1999, 37 ANN P INT REL PHY, P19

[8] High density platinum nanocrystals for non-volatile memory applications [J].

Dufourcq, J. ;

Bodnar, S. ;

Gay, G. ;

Lafond, D. ;

Mur, P. ;

Molas, G. ;

Nieto, J. P. ;

Vandroux, L. ;

Jodin, L. ;

Gustavo, F. ;

Baron, Th. .

APPLIED PHYSICS LETTERS, 2008, 92 (07)

[9] Photoluminescence studies of SiC nanocrystals embedded in a SiO2 matrix [J].

Guo, YP ;

Zheng, JC ;

Wee, ATS ;

Huan, CHA ;

Li, K ;

Pan, JS ;

Feng, ZC ;

Chua, SJ .

CHEMICAL PHYSICS LETTERS, 2001, 339 (5-6) :319-322

[10] Dependence of charge trapping and tunneling on the silicon-nitride (Si3N4) thickness for tunnel barrier engineered nonvolatile memory applications [J].

Jung, Myung-Ho ;

Kim, Kwan-Su ;

Park, Goon-Ho ;

Cho, Won-Ju .

APPLIED PHYSICS LETTERS, 2009, 94 (05)

← 1 2 3 →