SRAM operational voltage shifts in the presence of gate oxide defects in 90 nm SOI

The continued scaling of gate oxide thickness in CMOS transistors has made dielectric integrity paramount to system functionality at low voltages. In this paper, the effect of gate oxide breakdown on the minimum operating voltage (Vdd(min)) of a six transistor SRAM cell has been examined. A new cell reliability model was developed to explain non-monotonic operational voltage shifts through product reliability stress. Through simulation it was determined that non-monotonic voltage shifts can occur if random gate defects counter existing SRAM cell asymmetries. Furthermore, it has been shown that monotonic voltage shifts can be created with significantly different magnitudes of gate oxide defects.