Error Correction of Transient Errors in a Sum-Bit Duplicated Adder by Error Detection

被引：3

作者：

Weidling, Stefan ^{[1
]}

Sogomonyan, Egor S. ^{[1
]}

Goessel, Michael ^{[1
]}

机构：

[1] Univ Potsdam, Dept Comp Sci, Potsdam, Germany

来源：

16TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2013) | 2013年

关键词：

fault tolerance; transient error; concurrent error detection; clock gating; code-disjoint partial duplication;

D O I：

10.1109/DSD.2013.95

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

In this paper it is shown how the method of error correction of transient errors in a combinational circuit by use of error detection codes can be implemented for a sum-bit duplicated adder, thereby the outputs of the adder circuit are stored in fault-tolerant memory elements which are supposed to be fault-tolerant master-slave flip-flops. The combinational sum-bit duplicated adder circuit is monitored by an on-line detection circuit based on both a parity code and a duplication code. The error detection signal indicating an error in the combinational adder circuit blocks the slave clock signal in the second half of the clock cycle. The previous correct state values of all the slave latches are preserved for the duration of the transient error. As soon as the transient error disappears, the system can continue to work from a correct state, and no complicated restart of the system is necessary.

引用

页码：855 / 862

页数：8

共 18 条

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