Grain boundary potential barrier inhomogeneities in low-pressure chemical vapor deposited polycrystalline silicon thin-film transistors

Arrhenius plots of conductivity in low-pressure chemical vapor deposited (LPCVD) polycrystalline silicon thin-film transistors (TFT's) are curved when the films are deposited at pressures below 40 mtorr. These deviations from straight lines are explained by spatial potential fluctuations over the grain boundary plane described by a Gaussian type distribution. When grain boundary inhomogeneities are not taken into account, the determined trap states density and the threshold voltage of the transistor are underestimated.