A statistical sampler for a new on-line analog test method

被引：4

作者：

Negreiros, M ^{[1
]}

Carro, L ^{[1
]}

Susin, AA ^{[1
]}

机构：

[1] Univ Fed Rio Grande do Sul, PPGC, Inst Informat, Porto Alegre, RS, Brazil

来源：

PROCEEDINGS OF THE EIGHTH IEEE INTERNATIONAL ON-LINE TESTING WORKSHOP | 2002年

关键词：

D O I：

10.1109/OLT.2002.1030188

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this work a new strategy to the on-line test Of analog circuits is presented. The technique presents a very low analog overhead and it is completely digital. For the System-on-Chip (SoC) environment, this allows the implementation of on-line test using processing power already present in the system As all the signal processing is done in the digital domain, it allows use of a purely digital tester or a digital BIST technique. The main principle of operation is based on the observation of statistical properties of the circuit under test. Due to the low analog power and performance overhead, the proposed technique can be used to analyze the output of several stages of complex analog systems without the use of switches or analog multiplexors, as no additional AD converter is needed. This paper presents the fundamentals of the proposed test method and some preliminary results concerning linear analog systems.

引用

页码：79 / 83

页数：5

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