Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection

被引:63
作者
Wang, X. Shawn [1 ]
Wang, Xin [2 ]
Lu, Fei [3 ]
Zhang, Chen [3 ]
Dong, Zongyu [3 ]
Wang, Li [3 ]
Ma, Rui [3 ]
Shi, Zitao [4 ]
Wang, Albert [3 ]
Chang, Mau-Chung Frank [1 ]
Wang, Dawn [5 ]
Joseph, Alvin [5 ]
Yue, C. Patrick [6 ]
机构
[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA
[2] OmniVis Technol Inc, San Jose, CA 95148 USA
[3] Univ Calif Riverside, Dept Elect Engn, Riverside, CA 92521 USA
[4] Marvell Semicond, Shanghai 201203, Peoples R China
[5] IBM Microelect, Essex, VT 05452 USA
[6] Hong Kong Univ Sci & Technol, Clear Water Bay, Hong Kong, Peoples R China
关键词
CMOS; co-design; concurrent design; ESD; linearity; RF; SOI; SP10T; SPMT; switch; ANTENNA SWITCH; T/R SWITCH; CMOS;
D O I
10.1109/JSSC.2014.2331956
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper discusses concurrent design and analysis of the first 8.5 kV electrostatic discharge (ESD) protected single-pole ten-throw (SP10T) transmit/receive (T/R) switch for quad-band (0.85/0.9/1.8/1.9 GHz) GSM and multiple-band WCDMA smartphones. Implemented in a 0.18 mu m SOI CMOS, this SP10T employs a series-shunt topology for the time-division duplex (TDD) transmitting (Tx) and receiving (Rx), and frequency-division duplex (FDD) transmitting/receiving (TRx) branches to handle the high GSM transmitter power. The measured P-0.1 dB, insertion loss and Tx-Rx isolation in the lower/upper bands are 36.4/34.2 dBm, 0.48/0.81 dB and 43/40 dB, respectively, comparable to commercial products with no/little ESD protection in high-cost SOS and GaAs technologies. Feed-forward capacitor (FFC) and AC-floating bias techniques are used to further improve the linearity. An ESD-switch co-design technique is developed that enables simultaneous whole-chip design optimization for both ESD protection and SP10T circuits.
引用
收藏
页码:1927 / 1941
页数:15
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