A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling With Background Sampling-Point Calibration

被引：10
作者：
Tseng, Chien-Jian [1 ]
Lai, Chieh-Fan
Chen, Hsin-Shu
机构：
[1] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2014年 / 61卷 / 10期
关键词：
Background calibration; incomplete settling; pipeline analog-to-digital converter; power efficiency; A/D CONVERTER; DESIGN; CAPACITOR;
D O I：
10.1109/TCSI.2014.2333672
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 6-bit 1 GS/s single-channel pipeline ADC using an incomplete settling concept is presented. A background sampling-point calibration is proposed to adjust MDAC sampling point so that low gain and low bandwidth opamp can be utilized to conserve power. The prototype ADC in 65-nm CMOS process exhibits an INL of +0.76/-0.68 LSB and a DNL of +0.72/-0.68 LSB. Its ENOB is 5.25 bits at Nyquist input frequency with the conversion rate of 1 GS/s. It consumes 62 mW including calibration circuit power at 1 V supply and occupies an active chip area of 0.3 mm(2).
引用
收藏
页码：2805 / 2815
页数：11
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