Tunning of Phase Locked Loops for Power Converters under Distorted Utility Conditions

This paper analyzes the tuning of the phase locked loops (PLLs) employed in the control of power converters when there is distortion in the AC mains. The pros and cons of different optimization approaches are studied. In a general way, PLLs with a low bandwidth (low-gain PLLs) are required when handling with distorted. This paper proves that the tuning of low-gain PLLs have more than one trade-off. Besides the well known filtering versus transients response, it is also proved the existence of a trade-off between the response to phase-jumps and frequency variations: it is not possible to optimized the settling time for a phase step without getting slower the PLL response to frequency variations. All of issues should be taken into account for a correct tuning of the PILL, since a big part of the control of a power converters is in the synchronization algorithm. Experimental results obtained through a digital implementation (dSpace DS1103) validates the theoretical approach.