A 2.4-GHz RF Fractional-N Synthesizer With BW=0.25 fREF

被引：23

作者：

Kong, Long ^{[1
]}

Razavi, Behzad ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2018年 / 53卷 / 06期

关键词：

Sigma Delta noise; finite impulse response (FIR) filter; fractional-N synthesizer; loop bandwidth (BW); phase-locked loop (PLL); SUBSAMPLING PLL; BANDWIDTH; CMOS; LOOP;

D O I：

10.1109/JSSC.2018.2796544

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A fractional-N synthesizer architecture incorporates a 35-tap finite impulse response filter that suppresses the Sigma Delta noise, but does not affect the loop bandwidth (BW). Employing a three-stage ring oscillator and operating with a 22.6-MHz reference frequency, the synthesizer achieves a BW of around 5.6 MHz with a power consumption of 10 mW. Realized in 45-nm digital CMOS technology, the synthesizer exhibits a phase noise of -121.4 dBc/Hz at 10-MHz offset and an integrated jitter of 1.5 ps(rms).

引用

页码：1707 / 1718

页数：12

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