Role of gate oxide thickness in controlling short channel effects in polycrystalline silicon thin film transistors

被引：14

作者：

Valletta, A. ^{[1
]}

Gaucci, P. ^{[1
]}

Mariucci, L. ^{[1
]}

Pecora, A. ^{[1
]}

Cuscuna, M. ^{[1
]}

Maiolo, L. ^{[1
]}

Fortunato, G. ^{[1
]}

Brotherton, S. D. ^{[2
]}

机构：

[1] CNR, IMM, I-00133 Rome, Italy

[2] TFT Consultant, Forest Row RH18 5HB, England

来源：

APPLIED PHYSICS LETTERS | 2009年 / 95卷 / 03期

关键词：

elemental semiconductors; numerical analysis; semiconductor device models; silicon; thin film transistors;

D O I：

10.1063/1.3177196

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

The drain bias induced threshold voltage variation in short channel (L=0.4 mu m) polycrystalline silicon thin-film transistors (TFTs), with different gate oxide thicknesses, is investigated with combined experimental measurements and numerical simulations. Drain-induced barrier lowering (DIBL) and floating body effects (FBEs), triggered by impact ionization, are the main causes of such variations. However, the effects are counterbalancing, with a reducing oxide thickness reducing DIBL, while, at the same time, increasing the relative impact of the FBE. Hence, drain bias induced threshold voltage changes, when normalized by oxide thickness, are independent of the gate oxide thickness in these TFTs.

引用

页数：3

共 10 条

[1] High-speed, short-channel polycrystalline silicon thin-film transistors [J].