A Clock-less 8-bit Folding A/D Converter

被引：39

作者：

Rodrigues, S. A. ^{[1
]}

Accioly, J. I. C. ^{[1
]}

Aboushady, H. ^{[2
]}

Louerat, M. M. ^{[2
]}

Belfort, D. R. ^{[2
]}

Freire, R. C. S. ^{[3
]}

机构：

[1] Fed Inst Educ Sci & Technol IFPB, Elect Engn Coordinat, Joao Pessoa, Paraiba, Brazil

[2] Univ Paris 06, Lab LIP6, Paris, France

[3] Fed Univ Campina Grande UFCG, Dept Elect Engn, Campina Grande, Paraiba, Brazil

来源：

2010 FIRST IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS) | 2010年

关键词：

Analog-to-Digital Converter; Continuous-Time; Clock-less; Asynchronous; CMOS;

D O I：

10.1109/NOCS.2010.12

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper presents a continuous-time 8-bit folding analog-to-digital converter. The clock-less architecture is composed of 8 identical stages with 1 bit/stage. The circuit is designed in a 350nm CMOS process with a supply voltage of 3.3V. Simulation results show that the 8-bit clock-less ADC can achieve a Signal-to-Noise and Distortion Ratio of 53dB. The ADC has a power consumption of 5.51mW. The proposed circuit is compared with a similar continuous-time 8-bit pipeline ADC with 1 bit/stage.

引用

页码：25 / 28

页数：4