A 250-MHz Pipelined ADC-Based fS/4 Noise-Shaping Bandpass ADC

被引：9

作者：

Sarma, Vineeth ^{[1
,2
]}

Jacob, Nevin Alex ^{[1
]}

Sahoo, Bibhu Datta ^{[1
,3
]}

Narayanaswamy, Venkateswaran ^{[2
]}

Choudhary, Vikas ^{[2
,4
]}

机构：

[1] Amrita Univ, Amritapuri 690525, India

[2] Analog Devices Pvt Ltd, Bangalore 560016, Karnataka, India

[3] Univ Illinois, Champaign, IL 61801 USA

[4] Analog Devices Inc, Wilmington, MA 01887 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2018年 / 65卷 / 06期

关键词：

Sigma-delta; error-feedback; residue; quantization noise; pipelined ADC; noise shaping; DELTA-SIGMA MODULATOR; MHZ IF; THERMAL-NOISE; CMOS ADC; DB; MW; 10.7-MHZ; BANDWIDTH; RECEIVER; DESIGN;

D O I：

10.1109/TCSI.2017.2766883

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new f(S)/4 bandpass Delta Sigma-analog-to-digital converter (ADC) architecture is realized by feeding back the delayed quantization noise inherently produced by a pipelined ADC. Designed in a 55-nm global foundry (GF) LP-CMOS process, the prototype ADC sampling at 250 MHz achieves an Signal-to-Noise+Distortion Ratio of 72, 75.8, 80.1, and 85.3 dB in a 15.64-, 7.82-, 3.91-, and 1.953-MHz band, respectively, around a center frequency of 62.5 MHz with only first-order noise shaping, while consuming 103 mW of power, and achieving a maximum figure-of- merit of 158 dB.

引用

页码：1785 / 1794

页数：10

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