A 0.012 mm2 and 2.5 mW bang-bang digital PLL using pseudo random number generator

This paper present an area-efficient, low power, and fast lock-time digital PLL implemented in a 32 nm digital CMOS process by adopting a newly proposed bang-bang phase and frequency detector (BB-PFD) and integrated pseudo-random number generator (PRNG). The proposed BB-PFD is fully synthesizable, simply and easily implemented, and has a fast lock-time behavior. The integrated PRNG reduces the chip area and suppresses the spurious tones of the DCO phase noise caused by the periodic signal patterns from an accumulator output. In the proposed digital PLL, the measured lock-time with a high gain of 16 is approximately 9 times faster than without high gain mode. The PRNG suppresses the fractional dithering spur without degrading the DCO phase noise. The current consumption is 3 mA with a 0.85 V supply at 1.5 GHz. The total circuit area is 140 mu m x 80 mu m.