Proposal of Vertical-Channel Metal Oxide Semiconductor Field-Effect Transistor with Entirely Oxidized Silicon Beam Isolation

被引:1
作者
Sugimura, Atsushi [1 ]
Okuyama, Kiyoshi [1 ]
Sunami, Hideo [1 ]
机构
[1] Hiroshima Univ, Res Inst Nanodevice & Bio Syst, Hiroshima 7398527, Japan
关键词
Active regions - Local oxidation of silicons - Oxidized silicon - Self aligned structure - Silicon beams - Silicon pillar - Vertical channels - Vertical-channel transistors;
D O I
10.1143/JJAP.48.04C049
中图分类号
O59 [应用物理学];
学科分类号
摘要
A novel vertical-channel metal oxide semiconductor field-effect transistor (MOSFET) is successfully developed. This transistor features a highly self-aligned structure consisting of an active region, field oxide, and two sidewall gates. The active regions of silicon pillars and field oxides are formed in a straight silicon beam by the local oxidation of silicon (LOCOS). Subsequently, two sidewall gates are formed on a pillar as residues after controlled dry etching in a self-aligned manner. Since the two sidewall gates can control two different channels separately on one silicon pillar, two transistors are formed on the pillar. As the theoretical footprint of one pillar transistor is 4F(2), the proposed oxidized silicon beam isolated vertical-channel transistor (OBI-VCT) has a potential application to 2F(2)-footprint transistors, where F is feature size. (C) 2009 The Japan Society of Applied Physics
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页数:4
相关论文
共 9 条
[1]  
CHOI YK, 2001, IEDM, P437
[2]   A folded-channel MOSFET for deep-sub-tenth micron era [J].
Hisamoto, D ;
Lee, WC ;
Kedzierski, J ;
Anderson, E ;
Takeuchi, H ;
Asano, K ;
King, TJ ;
Bokor, J ;
Hu, CM .
INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :1032-1034
[3]  
Huang X., 1999, IEDM, P67, DOI [DOI 10.1109/IEDM.1999.823848, 10.1109/iedm.1999. 823848]
[4]  
Kedzierski J., 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), p19.5.1, DOI 10.1109/IEDM.2001.979530
[5]  
Richardson W. F., 1985, International Electron Devices Meeting. Technical Digest (Cat. No. 85CH2252-5), P714
[6]  
SUGIMURA A, 2008, EXT ABSTR INT C SOL, P418
[7]  
SUNAMI H, 1983, Patent No. 2069347
[8]   Development of three-dimensional MOS structures from trench-capacitor DRAM cell to pillar-type transistor [J].
Sunami, Hideo .
2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, :853-856
[9]  
Takato H., 1988, International Electron Devices Meeting. Technical Digest (IEEE Cat. No.88CH2528-8), P222, DOI 10.1109/IEDM.1988.32796