Bottom-up methodology for predictive simulations of self-heating in aggressively scaled process technologies

被引：0

作者：

Singh, D. ^{[1
]}

Restrepo, O. D. ^{[1
]}

Manik, P. P. ^{[1
]}

Mavilla, N. Rao ^{[1
]}

Zhang, H. ^{[1
]}

Paliwoda, P. ^{[1
]}

Pinkett, S. ^{[1
]}

Deng, Y. ^{[1
]}

Silva, E. Cruz ^{[1
]}

Johnson, J. B. ^{[1
]}

Bajaj, M. ^{[1
]}

Furkay, S. ^{[1
]}

Chbili, Z. ^{[1
]}

Kerber, A. ^{[1
]}

Christiansen, C. ^{[1
]}

Narasimha, S. ^{[1
]}

Maciejewski, E. ^{[1
]}

Samavedam, S. ^{[1
]}

Lin, C. -H. ^{[1
]}

机构：

[1] GLOBALFOUNDRIES Inc, 400 Stonebreak Rd Extens, Malta, NY 12020, Malta

来源：

2018 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2018年

关键词：

Self heating; FinFET; ab-initio; TCAD; Wiedemann-Franz law; Electromigration; Joule heating; SCATTERING;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present a hierarchical methodology using a combination of ab-initio phonon scattering, electron transmission, and multi-scale finite element simulations to accurately model process specific material physics and component level self-heating in FinFET technologies. The framework is applied to explain key heat transfer pathways and thermal resistance of FinFETs, interconnects and integrated precision resistors. Excellent agreement with thermal resistance measurements and its dependence on process technology is demonstrated across many device types without any fitting. The proposed methodology enables rapid systematic evaluation and process mitigation of self-heating in advanced CMOS technologies.

引用

页数：7

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