Cross-Coupled Dynamic CMOS Latches: Scalability Analysis

This paper primarily focuses on the power dissipation of cross coupled CMOS dynamic latches and also takes the technology scalability of the design into account. Mainly 3 topologies namely the Cascade Voltage Switch Logic (CVSL), Dynamic Single Transistor Clocked (DSTC) and Dynamic Ratio Insensitive (DRIS) have been investigated. A comparative study is provided which validates the suitability of the above latches for high-speed low power applications. Further, a brief account regarding the use of these latches for the design of high speed edge triggered flip-flops is also provided. The simulations results have been extensively verified on SPICE simulator using TSMC's industry standard 180 nm technology model parameters and the technology scalability is tested with 22 nm predictive technology model developed by Nanoscale Integration and Modeling (NIMO) Group of Arizona State University (ASU).