A 25-gb/s CDR in 90-nm CMOS for high-density interconnects

This paper presents a clock-and-data recovery (CDR) for pseudo-synchronous high-density link applications. The CDR is a first-order bang-bang (BB) topology implemented in a standard CMOS process and consists of a phase interpolator, a linear half-rate phase detector, an analog filter followed by a limiter and a digital loop filter operating at a reduced clock rate. A detailed BB CDR analysis derives the maximum tracking range, slew-rate limited jitter tolerance and maximum loop delay. The circuit is optimized for high speed as well as low area and power consumption. The CDR operates from 8-28 Gb/s at a BER of < 10(-12) and tracks frequency deviations between the incoming data and the reference clock of up to 122 ppm. The sinusoidal jitter tolerance is > 0.35 UIpp for jitter frequencies <= 100 MHz and the to jitter of the recovered half-rate output data amounts to 0.22 UIpp at a BER = 10(-12). The core CDR circuit occupies a chip area of 0.07 mm(2) and consumes 98 mW from a 1.1-V supply.