Efficient Floating-Point Implementation of the Probit Function on FPGAs

被引:1
作者
Joldes, Mioara [1 ]
Pasca, Bogdan [2 ]
机构
[1] CNRS, LAAS, Toulouse, France
[2] Intel Corp, Toulouse, France
来源
2020 IEEE 31ST INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 2020) | 2020年
关键词
Floating-point arithmetic; FPGA; quantile; inverse error function;
D O I
10.1109/ASAP49362.2020.00036
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Non-uniform random number generators are key components in Monte Carlo simulations. The inverse cumulative distribution function (ICDF) technique provides a viable solution for generating random variables from various distributions. Thus, the ICDF of the standard normal distribution, or probit function for short, is of particular interest. The goal of this article is to revisit and improve a floating-point (FP) implementation of probit, from the perspective of modern hardware resources available on FPGAs. Beside reexamining the classical Wichura's algorithm, we propose: (1) a single-precision implementation using the embedded FP DSP Blocks available in recent FPGA families; (2) generic custom-precision architectures that scale up to double-precision. These present a user-selectable trade-off between tail accuracy and resource utilization. Our proposed cores outperform existing single-precision FPGA implementations in area, latency and accuracy, and also set benchmarks for new custom and double-precision FP implementations.
引用
收藏
页码:173 / 180
页数:8
相关论文
共 18 条
[1]  
AGBO IO, 2019, INT TEST CONF P
[2]  
[Anonymous], 2018, INTEL ARRIA DEVICE O
[3]   Hardware generation of arbitrary random number distributions from uniform distributions via the inversion method [J].
Cheung, Ray C. C. ;
Lee, Dong-U ;
Luk, Wayne ;
Villasenor, John D. .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2007, 15 (08) :952-962
[4]  
Chevillard S, 2010, LECT NOTES COMPUT SC, V6327, P28, DOI 10.1007/978-3-642-15582-6_5
[5]   Certification of Bounds on Expressions Involving Rounded Operators [J].
Daumas, Marc ;
Melquiond, Guillaume .
ACM TRANSACTIONS ON MATHEMATICAL SOFTWARE, 2010, 37 (01)
[6]  
de Dinechin F., 2010, Proceedings of the 21st IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2010), P216, DOI 10.1109/ASAP.2010.5540952
[7]  
de Schryver C., 2010, Proceedings 2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2010), P190, DOI 10.1109/ReConFig.2010.20
[8]  
Echeverría P, 2007, MIDWEST SYMP CIRCUIT, P727
[9]   MPFR: A multiple-precision binary floating-point library with correct rounding [J].
Fousse, Laurent ;
Hanrot, Guillaume ;
Leflvre, Vincent ;
Plissier, Patrick ;
Zimmermann, Paul .
ACM TRANSACTIONS ON MATHEMATICAL SOFTWARE, 2007, 33 (02)
[10]  
Hormann W., 2003, ACM Transactions on Modeling and Computer Simulation, V13, P347, DOI 10.1145/945511.945517