Design of a precision Timer Based on CPLD

被引：0

作者：

Wang Jianxin ^{[1
]}

Gao Xianwei ^{[1
]}

Li Xiuying ^{[1
]}

Sui Meili ^{[2
]}

机构：

[1] Beijing Elect Sci & Technol Inst, Dept Elect & Informat Engn, Beijing, Peoples R China

[2] Chinese Acad Sci, Beijing Senior Expert Technol Ctr, Beijing, Peoples R China

来源：

2011 INTERNATIONAL CONFERENCE ON FUTURE INFORMATION ENGINEERING (ICFIE 2011) | 2011年 / 8卷

关键词：

CPLD; timer; Verilog HDL;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

CPLD is digital integrated circuits, which can be constructed logic functions by the users themselves according to their respective demands. From the actual needs, this paper researches a timer based on CPLD, building the circuit schematic diagram from the system structure diagram, using Verilog HDL for system programming, emulating the functions of system keys in the Quartus II integrated development environment. The simulation results show that the system can achieve the intended functions and indicators, which provides some reference for the construction of digital systems.

引用

页码：176 / 181

页数：6

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