Convolutional neural network acceleration with hardware/software co-design

被引：10

作者：

Chen, Andrew Tzer-Yeu ^{[1
]}

Biglari-Abhari, Morteza ^{[1
]}

Wang, Kevin I-Kai ^{[1
]}

Bouzerdoum, Abdesselam ^{[2
,3
]}

Tivive, Fok Hing Chi ^{[2
]}

机构：

[1] Univ Auckland, Dept Elect & Comp Engn, Auckland, New Zealand

[2] Univ Wollongong, Sch Elect Comp & Telecommun Engn, Wollongong, NSW, Australia

[3] Hamad Bin Khalifa Univ, Coll Sci & Engn, Doha, Qatar

来源：

APPLIED INTELLIGENCE | 2018年 / 48卷 / 05期

关键词：

Computer vision; Embedded system; Neural network; Co-design; Hardware acceleration; FPGA; Real-time; Gender recognition; GENDER; ARCHITECTURE; SYSTEM; RESOLUTION; FUSION;

D O I：

10.1007/s10489-017-1007-z

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Convolutional Neural Networks (CNNs) have a broad range of applications, such as image processing and natural language processing. Inspired by the mammalian visual cortex, CNNs have been shown to achieve impressive results on a number of computer vision challenges, but often with large amounts of processing power and no timing restrictions. This paper presents a design methodology for accelerating CNNs using Hardware/Software Co-design techniques, in order to balance performance and flexibility, particularly for resource-constrained systems. The methodology is applied to a gender recognition case study, using an ARM processor and FPGA fabric to create an embedded system that can process facial images in real-time.

引用

页码：1288 / 1301

页数：14

共 50 条

[1] Convolutional neural network acceleration with hardware/software co-design
Andrew Tzer-Yeu Chen
Morteza Biglari-Abhari
Kevin I-Kai Wang
Abdesselam Bouzerdoum
Fok Hing Chi Tivive
Applied Intelligence, 2018, 48 : 1288 - 1301
[2] Convolutional Neural Network Model Compression Method for Software-Hardware Co-Design
Jang, Seojin
Liu, Wei
Cho, Yongbeom
INFORMATION, 2022, 13 (10)
[3] Software/Hardware Co-Design Optimization for Sparse Convolutional Neural Networks
Hu, Wei
Dong, Yong
Liu, Fang
Jiao, Qiang
2021 IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN, AND CYBERNETICS (SMC), 2021, : 2069 - 2074
[4] From Model to FPGA: Software-Hardware Co-Design for Efficient Neural Network Acceleration
Guo, Kaiyun
Sui, Lingzhi
Qui, Jiantao
Yao, Song
Han, Song
Wang, Yu
Yang, Huanzhang
2016 IEEE HOT CHIPS 28 SYMPOSIUM (HCS), 2016,
[5] Hardware-Software Co-design to Accelerate Neural Network Applications
Imani, Mohsen
Garcia, Ricardo
Gupta, Saransh
Rosing, Tajana
ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 2019, 15 (02)
[6] ASBNN: Acceleration of Bayesian Convolutional Neural Networks by Algorithm-hardware Co-design
Fujiwara, Yoshiki
Takamaeda-Yamazaki, Shinya
2021 IEEE 32ND INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 2021), 2021, : 226 - 233
[7] Acceleration of software algorithms using hardware/software co-design techniques
Edwards, MD
Forrest, J
Whelan, AE
JOURNAL OF SYSTEMS ARCHITECTURE, 1997, 42 (9-10) : 697 - 707
[8] Software-Hardware Co-design for Video Coding Acceleration
Niu, Xinwei
Galarza, Luis
Gao, Ying
Fan, Jeffrey
2012 44TH SOUTHEASTERN SYMPOSIUM ON SYSTEM THEORY (SSST), 2012, : 57 - 60
[9] HARDWARE/SOFTWARE CO-DESIGN USING ARTIFICIAL NEURAL NETWORK AND EVOLUTIONARY COMPUTING
Dias, Mauricio Acconcia
Lacerda, Wilian Soares
2009 5TH SOUTHERN CONFERENCE ON PROGRAMMABLE LOGIC, PROCEEDINGS, 2009, : 153 - 157
[10] Hardware/software co-design
De Micheli, Giovanni
Gupta, Rajesh K.
Proceedings of the IEEE, 1997, 85 (03): : 349 - 365

← 1 2 3 4 5 →